Atomera: Increasing TAM, But Still Speculative

Atomera Incorporated advances MST technology for next-gen semiconductors, targeting GAA, GaN, and memory markets. Read more ...
The Economist

The future of chipmaking looks more like Manhattan than Silicon Valley

D rive around Silicon Valley and you will see surprisingly little skyline. The landscape is dotted with low-rise offices, ...
IEEE

Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling

Abstract: 2-D materials show promise to possibly replace Si channel material to continue Moore’s Law scaling of transistors down to 5 nm gate lengths. The scaling opportunities of 2-D materials arise ...

2D semiconductors & 2 Angstrom: Chip roadmap for Europe until 2041

Imec presents an updated roadmap for high-end chip manufacturing. From 2031, CFET transistors are set to replace GAA-FET ...
Electronic Design

IBM 7-Angstrom Tech Squeezes in 100 Billion Transistors

Smaller transistors usually mean better performance and greater power efficiency. In this case, the new 7-Å devices bump up performance by 50% while improving power utilization by 70% compared to ...
DatacenterDynamics

Onsemi acquires neural network technology company Synaptics in $7bn all-stock deal

The deal comes almost a year after Onsemi acquired Aura Semiconductor’s Vcore power technologies for an undisclosed amount.
Interesting Engineering

‘World’s first’: IBM packs 100 billion transistors into a fingernail-sized sub-1 nm chip

IBM has introduced what it calls the world’s first sub-1 nanometer semiconductor technology, unveiling a 0.7 nm chip built on a new three-dimensional transistor architecture designed to extend chip ...
IEEE Spectrum on MSN

Future transistor stacking plans start to diverge

IBM chooses a different path from Intel, Samsung, and TSMC ...

Samsung Electronics Implements 'Vertically Stacked Transistor' at World’s Top Semiconductor Conference... Wins Best Paper

Samsung Electronics has pioneered a groundbreaking technology by vertically stacking transistors, which were previously arranged on a planar surface, ...

Intel unveils Intel 18A-P advancements at VLSI 2026 with up to 9% performance boost and 18% lower power consumption

Intel has announced a series of updates to its semiconductor manufacturing roadmap at the 2026 VLSI Symposium, including the entry of its Intel 18A-P process technology into risk production. The ...
IEEE

One-Ferroelectric-Tunnel-FET-Based Reconfigurable Logic Gates

Abstract: A novel reconfigurable logic gate (RLG) utilizing one ferroelectric tunnel field-effect transistor (FeTFET) is proposed for the first time. By leveraging the symmetric ambipolar current of ...